1. Field of the Invention
The present invention relates generally to a CCD circuit and more particularly is directed to an output signal processing circuit for a CCD register.
2. Description of the Prior Art
A solid-state image pickup apparatus comprising charge transfer device such as charge coupled device (CCD) has a photo-sensitive part to perform photoelectric conversion, a charge transfer part to transfer the signal charge obtained in the photo-sensitive part, and an output part for delivering an output signal based on the transferred signal charge. In an interline transfer system, for example, the signal charge from each photoelectric cell is transferred via a transfer gate to a light-shielded vertical register, and the signal charges are sent out sequentially from the vertical registers to light-shielded horizontal registers, so that an image pickup signal is obtained via an output circuit of a CCD register connected to the horizontal registers.
The conventional output circuit of a CCD register known heretofore has a constitution shown in FIG. 1. Denoted by 31 and 33 in this circuit diagram are a horizontal register and a horizontal output gate, respectively. The horizontal register 31 is supplied with, for example, two-phase clock pulses .phi.1 and .phi.2 from terminals 32A and 32B respectively. Meanwhile the horizontal output gate 33 is supplied with a bias voltage of a predetermined level from a terminal 34. The drain-source of a field effect transistor 36 constituting a floating diffusion amplifier is inserted between the horizontal output gate 33 and a power supply terminal 35, and a capacitor 38 is formed equivalently between the horizontal output gate 33 and the ground. A precharge pulse P.sub.p synchronized with the transfer clock pulses .phi.1 and .phi.2 is supplied from a terminal 37 connected to the gate of the field effect transistor 36. The image pickup output signal obtained at the junction of the source of the field effect transistor 36 and the capacitor 38 is delivered to an output terminal 42 via a two-stage source follower circuit which consists of field effect transistors 39 and 40, and an emitter follower circuit consisting of a bipolar transistor 41.
FIG. 2 graphically shows the relationship among the two-phase transfer clock pulses .phi.1 and .phi.2, the precharge pulse P.sub.p, and the output voltage Vo produced at one terminal of the capacitor 38.
FIG. 3A shows the electrode structure of the output circuit of FIG. 1, and FIGS. 3B, 3C and 3D show the potentials at different instants t1, t2 and t3 in FIG. 2 respectively. As is obvious from FIG. 3A, the horizontal register 31 has such an electrode structure as to transfer the signal charges Sn, Sn+1 and so forth rightward from the left hand in accordance with the two-phase clock pulses. The field effect transistor 36 has a floating diffusion region 43, a precharge gate 44 and a precharge drain 45 which correspond respectively to the source, gate and drain of the transistor 36 shown in FIG. 1.
Referring now to FIGS. 2 and 3, a description will be given below of how a CCD output signal is taken out. First, the field effect transistor 36 is turned on during the precharge time Tp in which a precharge pulse Pp is supplied to the gate of the field effect transistor 36 in a state where the pulse .phi.1 is at a high level while the pulse .phi.2 is at a low level. The relationship among the individual potentials at the instant (t=t1) within the precharge time Tp is such that, as shown in FIG. 3B, the potential of the precharge gate 44 is low. When the field effect transistor 36 is turned on, the capacitor 38 is charged immediately by the supply voltage Vb impressed to the terminal 35. And simultaneously the precharge pulse Pp fed to the gate of the field effect transistor 36 appears at the source side thereof through the parasitic capacitance formed substantially between the gate and source of the field effect transistor 36. Consequently, at one terminal of the capacitor 38, there is generated an output voltage Vo where the voltage Vp of the precharge pulse Pl is superimposed on the supply voltage Vb.
The precharge time Tp is followed by a reference potential time To which is immediately before the charge transfer from the horizontal register 31 to the output circuit. In this referential potential time To during which the precharge pulse Pp is at a low level, the field effect transistor 36 is kept in its off-state. Accordingly the output voltage Vo at one terminal of the capacitor 38 is lowered, in comparison with the value during the precharge time To, by the voltage Vp of the precharge pulse Pp to consequently become equal to the supply voltage (reference level) Vb. At the instant (t=t2) in the reference potential time To, as shown in FIG. 3C, the potential of the precharge gate 44 is raised while the potential of the floating diffusion region 43 is rendered equal to the reference potential.
Next to the reference potential time To is a transfer time Tt during which the pulse .phi.1 is at a low level and the pulse .phi.2 at a high level. In the transfer time Tt, there is obtained an output voltage Vo of the data signal voltage Vs corresponding to the signal charge Sn transferred from the horizontal register 31. The individual potentials at the instant (t =t3) in the transfer time Tt are such as those shown in FIG. 3D. Thus, the signal charge Sn is transferred to the floating diffusion region 43.
When the output voltage Vo is delivered as described above, the charge in the source-drain region (precharge gate region 44) of the field effect transistor 36 is moved between the floating diffusion region 43 and the precharge drain region 45 in the precharge time Tp (FIG. 3D), so that the potential of the floating diffusion region is forcibly equalized to the potential of the precharge drain region 45 and is thereby maintained in a stable state. Consequently the charge state immediately before turn-off of the precharge gate region 44 is not rendered constant, and therefore when the precharge gate region 44 is turned off as shown in FIG. 3C, a reset noise component .DELTA.n is contained in the floating diffusion region 43. Since the level of such reset noise component .DELTA.n becomes different depending on the periods, there occurs, among the individual transfer periods, a difference of the referential potential (feed-through level) in the reference potential time To. As a result, when the signal charge Sn is transferred during the transfer time Tt, it follows that, as shown in FIG. 3D, the reset noise .DELTA.n is superposed on the signal charge Sn and is therefore contained also in the output voltage Vo.
The reset noise mentioned above is termed white noise, and the number Nr of its noise electrons is given by the following equation. EQU Nr=.sqroot./k T Cf/q
where Cf is the capacitance of the floating diffusion region 43.
In addition to such reset noise, there are so-called 1/f noise and thermal noise generated in the source follower stages of the field effect transistors 39 and 40. In the 1/f noise, the noise level rises in inverse proportion to the frequency. Meanwhile, the thermal noise is high-frequency white noise.
In an attempt to remove such noises, there is proposed a contrivance as disclosed in, for example, Japanese Patent Laid-open No. 56(1981)-116374, wherein a correlated double sampling process is executed for the CCD output signal obtained from a solid-state image pickup apparatus so as to provide a satisfactory output video signal where the harmful influence of the level variation in the reference level portion of the CCD output signal has been compensated for.
FIG. 4 is a block diagram of the output signal processing circuit described in the above Japanese patent publication. In this diagram, a CCD output signal SV of FIG. 5A is fed to an input terminal 51, and the signal SV is further fed to each of sample-and-hold circuits 52 and 53. The circuit 52 samples and holds the CCD output signal SV in accordance with a sampling pulse SP1 of FIG. 5B received from a terminal 54. The sampling pulse SP1 has a phase corresponding to the reference level portion of the CCD output signal SV obtained during the reference potential time To, so that the sample-and-hold circuit 52 produces an output signal coincident in level with the reference level portion in each transfer period. The output signal of the sample-and-hold circuit 52 is fed further to a sample-and-hold circuit 55.
Meanwhile the sample-and-hold circuit 53 performs its operation in accordance with a sampling pulse SP2 of FIG. 5C received from a terminal 56. The sampling pulse SP2 has a phase corresponding to the information signal portion of the CCD output signal SV obtained during the transfer time Tf, so that the sample-and-hold circuit 53 produces an output signal coincident in level with the information signal portion in each transfer period. The output signal of such sample-and-hold circuit 53 is supplied to a subtracter 57. Further in the sample-and-hold circuit 55, the output signal of the circuit 52 is sampled and held in accordance with the sampling pulse SP2, and the output signal of the circuit 55 is supplied also to the subtracter 57.
In the subtracter 57, the output signal of the sample-and-hold circuit 55 is subtracted from that of the sample-and-hold circuit 53. Consequently, at an output terminal 58 connected to the output of the subtracter 57, there is obtained an output video signal posterior to removal of any level variation derived from the level variation in the reference level portion of the CCD output signal SV.
There is known another conventional constitution as disclosed in U.S. Pat. No. 3,781,574 where a reference level portion is clamped at a predetermined potential, then the image pickup output signal thus clamped is fed to a sample-and-hold circuit, and subsequently the level of the information signal portion is sampled and held.
The output signal processing circuit for each of such conventional CCDs is effective for removing the aforementioned reset noise and 1/f noise. However, since both of such known circuits are of the type that samples and holds also the high-frequency component above the Nyquist frequency, there occurs deterioration in the signal-to-noise ratio due to the aliasing of the high-frequency noise (thermal noise component). For the purpose of solving the above problem, there is proposed an integrated type correlated double sampling method described in "Journal of Television Society", Vol. 39, No. 12 (1985), pp. 1176 (38)-1181 (43). According to this system, the level of the reference level portion and that of the information signal portion are integrated respectively for a predetermined time, and the difference between the two integral values is calculated to achieve simultaneous removal of both the high-frequency noise component and the reset noise. Each of the integrating circuits is equipped with a reset switch actuated per period. The above integrated type correlated double sampling method is effective also for enhancing the modulation transfer function (MTF).
The aforementioned CCD output circuit shown in FIG. 1 serves as a charge-to-voltage converter which converts into a signal voltage the signal charge transferred cyclically from the CCD register. The CCD output signal obtained from the CCD output circuit contains an information signal voltage proportional to the charge stored per pixel discretely. FIG. 6A shows a discrete series of the CCD output signal per transfer period thereof, and FIG. 6B shows a frequency spectrum of the CCD output signal. As is obvious from FIG. 6B, the CCD output signal contains both a baseband component 46 and higher harmonic components 47 derived from the sampling.
As shown in FIG. 6C, the discrete CCD output signal is normally held until appearance of the information signal voltage of the next period in a manner termed zero-order hold. Due to such holding action, the information signal voltage of a discrete value is rendered processible as an ordinary baseband video signal. On the other hand, however, such holding action causes a disadvantage that, as represented by a one-dot chain line in FIG. 6D, the CCD output signal is affected by the sine function characteristic 48 where the sampling frequency fs (=1/T) is an initial zero with a curve expressed as sin (.pi.f/fs)/(.pi.f/fs), so that the modulation transfer function (MTF) in the vicinity of the frequency fs is deteriorated by the low-pass characteristic of the sine function to the band below the frequency fs.
According to the aforementioned integrated type correlated double sampling method which executes chopping of the CCD output signal by a reset switch, there is generated an output signal of the waveform shown in FIG. 6E. Supposing that the pulse has a duration .tau. in FIG. 6E, there occurs a low-pass characteristic 49 where the frequency 1/.tau. is an initial zero as represented by a one-dot chain line in FIG. 6F. Such sine function characteristic 49 has a curve expressed as sin (.pi.f.tau.)/(.pi.f.tau.), and its pass band is wider than that of the aforesaid sine function characteristic 48 shown in FIG. 6D, thereby preventing deterioration of the modulation transfer function in the vicinity of the frequency fs.
In the integrated type correlated double sampling that employs a reset switch, sufficient stability of the reset pulse itself is strictly required for actuating the reset switch. Therefore, troubles of fixed-pattern noise and shading are prone to occur due partially to modulation of a power supply for a reset pulse generator, and the noise is increased by jitters of reset pulses with another problem of harmful influence from interference of external electromagnetic waves and so on.